Recently, the density of semiconductor devices and operating speeds thereof have been increased. However, in case of a semiconductor integrated circuit having conventional one layer wiring, a reduction in the width of metal wiring in the memory device increased electrical resistance. Thus, the power consumption increases. Accordingly, to enhance operating speed, multilayer wiring has been proposed. A material metal wiring is aluminum containing silicon of under 4% to prevent aluminum spike occurred when forming wiring with pure aluminum. However, aluminum wiring containing added copper added has been proposed to improve reliability.
FIGS. 1A and 1B illustrate a conventional method for manufacturing a semiconductor device having multilayer wiring. In the FIG. 1A, on a semiconductor substrate 1 of a first conductivity type, where field oxide layer 3 for isolation is formed, a first insulation layer 5, a first conductive layer 7, a second insulation layer 9, a second conductive layer 11 and a third insulation layer 13 are consecutively deposited. Then, a contact hole 15 is formed through selective etching of the third insulation layer 13 by photolithography. Thus, the top surface of the second conductive layer 11 is partially exposed. Here, the first conductive layer 7 is bit line, and the second conductive layer 11 is aluminum wiring containing silicon of about 1% and copper of about 0.5%. By employing the above mentioned aluminum in the metal wiring, hillock and electromigration characteristics can be improved as compared with conventional aluminum wiring containing only silicon. The wiring made of the second conductive layer 11 and another wiring (not shown) are contacted through the contact hole 15. In forming the described wiring of multilayer structure, in practice, underlying layer wiring can be damaged by the chemical reaction of copper component extracted into the grain boundary of the aluminum, water (H.sub.2 O) and organic solvents, etc, which occur during removal of the ordinary photoresist. That is, to expose the surface of the underlying layer wiring, plasma ashing (process of developing a photoresist and thereafter removing the photoresist remaining after plasma etching process), dipping in an organic solvent such that sulfate acid, rinsing with water and drying are progressively carried out to remove the remaining photoresist positioned on the upper surface of the insulation layer. At this time, the exposed portions of aluminum wiring containing copper directly contact the organic solvent and water. As a result, the copper component existing in grain boundary of the aluminum is discolored with black spots and pieces of the second conductive layer 11 may drop away. The size of these pieces can be 1.mu.m in diameter. The resultant damage of the wiring is shown in the FIG. 1A. When an overlying layer wiring is formed by the vapor deposition and the underlying layer wiring is damaged, step coverage is inferior. Accordingly the overlying layer wiring is shorted or the contact area is decreased increasing contact resistance. Thus electrical characteristic of devices deteriorates.
FIG. 1B illustrates the cross sectional view of the conventional multilayer wiring. On the third conductive layer of aluminum, an overlying layer wiring 17 is disposed by formation of a pattern and selective etching. As shown in FIG. 1B, a portion of the overlying layer wiring contacting the underlying layer wiring small because of the interior step coverage.
As described above, conventional method has a problem that the wiring is damaged by exposure of the underlying layer wiring through the contact hole, when the remaining photoresist disposed over the underlying layer is removed after forming the contact hole on the underlying layer wiring. Therefore, reliable semiconductor integrated circuit is not obtained.